1) Field of the Invention
This invention relates generally to fabrication of a capacitor in a DRAM cell and more particularly to a method for fabricating stacked capacitors with a large capacitance and a high density.
2) Description of the Prior Art
Very large scale integration (VLSI) semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on semiconductor substrate are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device sized and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integration, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field effect transistor (MOS-FET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge. The decrease in cell capacitance caused by reduced memory cell area is a serious obstacle to increasing packing density in dynamic random access memories (DRAMs). Thus, the problem of decreased cell capacitance must be solved to achieve higher packing density in a semiconductor memory device, since decreased cell capacitance degrades read-out capability and increases the soft error rate of the memory cell as well as consumes excessive power during low-voltage operation by impeding device operation.
Generally, in a 64 MB DRAM having a 1.5 .mu.m.sup.2 memory cell area employing an ordinary two dimensional stacked capacitor cell, sufficient cell capacitance cannot be obtained even though a higher dielectric constant material, e.g., tantalum oxide (Ta.sub.2 O.sub.5), is used. Therefore, stacked capacitors having a three-dimensional structure have been suggested to improve cell capacitance. Such stacked capacitors include, for example double-stacked, fin-structured, cylindrical, spread-stacked, and box structured capacitors.
Workers in the art of aware of the challenges to produce small high capacitance DRAM capacitors. For example in U.S. Pat. No. 5,104,821 to Choi et al., a method is shown for forming a stacked capacitor having a bath tub shaped structure in which a bottom electrode is patterned from a first polysilicon layer using a first mask pattern. Next, a silicon nitride layer and a second polysilicon layer are formed over the bottom electrode. Then the silicon nitride layer and the second polysilicon layer are the etched using a second photo/etch step using a second masking pattern having a reverse phase of the first mask pattern. The second mask pattern must be aligned to the first mask pattern which adds overlay variation. The second polysilicon layer is oxidized forming an opening over the bottom electrode. Then the bottom electrode is etched through the opening to create a bathtub structure which has upwardly extended edges. The bathtub shaped bottom electrode is covered with a dielectric and top electrode to form a capacitor. However, this method can be improved to create an even smaller bottom electrode and provide better process control of the capacitance.
Also, many of the prior art methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. There is a challenge to develop methods of manufacturing these capacitors that minimize the manufacturing costs and maximize the device yields. In particular, there is a challenge to develop a method which minimizes the number of photoresist masking operations and provides maximum process tolerance to maximize product yields. There is also a challenge to develop a stacked capacitor which is not limited in size by the photolithographic resolution and alignment techniques.